تصميم منطقي الجزء الثاني cs105
course part 2
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Quiz2
- important Question 03:19
- QUIZ Ch3 New Blackboard 23:35
- Quiz2_exam3 22:15
- QUIZ2_EXAM1 30:17
- Quiz blackboard_ch3 10:21
- QUIZ_Blackboard_New 07:25
- CH3 NEW QUIZ 08:59
- Quiz2_Exam2 18:26
- Example ch3 08:34
- Extra_Blackboard 11:45
- Important _Example_Ch3 21:18
- practice chapter3 Q1,2,3,4 12:39
- practice chapter3 Q5,6,7,8,9,10 24:02
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MID2
- MID2 2024 33:27
- Example mid2 2024 05:50
- New Exam this term CH3,4 24:43
- MID2 2023 44:07
- MID2 2022 21:55
- MID2 2023 IMPORTANT 16:24
- mid2 2023 new* 11:08
- MID2 2023 3rd term 12:03
- MID2_NEW
- Extra_Exam_Mid2_Important
- EXAM MID2 NEW 12:35
- MID2 NEW EXAM 25:10
- Mid2_Exam3 17:42
- MID2_EXAM1 22:43
- MID2_EXAM2 24:12
- Revision_Ch4_Combinational Circuit
- Revision_adder_Multiplier 09:40
- Revision_CH4_Decoder-Multiplexer 23:45
- Example Binary Adder subtructor
- Revision Extra multiplexer,encoder,decoder 39:04
- Extra EXAMPLE CH4 02:31
- EXTRA_Question _MID2
- Revision Mid2 08:16
- Revision_Multiplchoice 30:07
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Experiment LAB
- Binary to Decimel Decoder 14:48
- OR,AND,NOR,NAND 21:17
- Example OR,AND 03:20
- Multiplexer 31:32
- Flip_Flop 21:38
- Experiment sheet 05:57
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CHAPTER 4
- Analysis circuit ,Design procedure 26:26
- Half A DDER, Full A adder 14:01
- Binary Adder Subtractor 16:58
- BCD Adder 10:32
- Multiplier 10:41
- Decoder 27:10
- Encoder 12:22
- Multiplexer 20:25
- EXCERSICE Chapter4 Q1,2 13:26
- EXCERCISE Chapter4 Q3,4 25:18
- HW SLIDE NO 21 16:00
- Exercise ch4 Q5 03:06
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Final Lab
- Example_combinational circuit 06:32
- EXAM_FINAL 13:17
- EXAM2_FINAL 03:21
- EXAM3_FINAL LAB 08:22
- Example_Implement_Decoder_Mux 04:34
- NEW _FINAL LAB 29:39
- Exam Mid, Final 30:00
- FiNAL LAB EXAM CH5 NEW
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Final revision
- Final Excercise 01:18:11
- EXAM CHAPTER 5 05:19
- final 2023 18:28
- Final lab2 06:52
- Final exam( important Question Ch5) 33:15
- Final important 25:54
- Final Important 2 21:58
- Final Online 28:15
- HOW TO LIST state table from state diagram 11:28
- Final_Revision 1 27:08
- FINAL_Revision 2 25:46
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Chapter 5
- S-R Latches 24:40
- Latching Timing Problem 11:47
- D-flipflop 23:33
- Slide design jk using D flip flop 02:05
- J-K Flip flop 15:36
- QUIZ BLACK BOARD_CH5 17:31
- Revision1 chapter 5 24:57
- Revision 2 Chapter 5
- Excercise Ch5 part1 40:42
- Excercise Ch5 part2 30:00
- HOW TO FIND equation by simple method 07:07
- QUIZ3 CH5 MULTIPLE CHOICE 04:32
- QUIZ CH5 2024 EXTRA 02:55
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NEW SHEET
- Sheet 4 New Part 1 15:49
- Sheet 4 New Part 2 10:49
- chapter4 drawing logisim (mux-halfadder) 13:53
- chapter4 logisim (decoder) 03:11
- SHEET 5 Q1,2,3 37:44
- SHEET 5 Q 4,5 21:11
- Sheet 4 extra part 1 35:44
- Sheeet4 extra example 15:49
- SHEET 4 extra PART 2 28:50
- Sheet 5 logisim Q1 02:16
- Sheet 5 extra 29:54
- SHEET 5 extra Q3 14:38
- Summary
- New Project
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Quiz2
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course part 2 -
My name is Sara I 'm electronic and communication engineer.
Sara Qualifications: Masters in Networks and Communications.
Sara Experiences:
1- professor at the National Institute of Communications for training computer network courses like CCNA ,CCNP , computer programs.
2- Sara experiences 8 years for teaching Princess Noura University subjects as :
* communications and network fundamentals It222
*computer network fundamentals it221
* Digital Logical design cs105
* Information Security it311
*advanced computer network net431
(All courses include an explanation of the slides + Tutorial solution + comprehensive summaries + an explanation of the Labs with assemblies for Final Lap + assemblies for quiz ,mid1,2 and final exam + solution and explanation of the project)
3- Sara Experience in teaching the subjects of King Saud University and the Imamu University subjects as : *The principles of computer networks (IT328) *Logical design cs106 (The courses include practical, theoretical and lab) -
Student feedback
5Course Rating
175 SAR
Lectures
110 Videos
Duration
30:50:27
Material
106 Files
Assignments
Yes, Completely
Labs
Yes, Completely
Project
Yes, Completely
Certificate
Not Applicable
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